This invention relates to phase alignment and clock recovery. More particularly, this invention relates to providing dynamic phase alignment and clock recovery circuitry.
Programmable logic resource technology is well known for its ability to allow a common hardware design (embodied in an integrated circuit) to be programmed to meet the needs of many different applications. Known examples of programmable logic resource technology include programmable logic devices (PLDs) and field programmable gate arrays (FPGAs).
To facilitate the use of programmable logic resources in certain applications, intellectual property (IP) blocks are coupled to programmable logic resource core circuitry. In one application, an IP block is a block of logic or data that supports a multi-channel communications protocol such as high speed serial interface (HSSI) communications. HSSI communications includes industry standards such as, for example, XAUI, InfiniBand, 1G Ethernet, FibreChannel, Serial RapidIO, and 10G Ethernet. In a multi-channel communications protocol, data transfers to and from the programmable logic resource core circuitry and the IP block over multiple channels. For example, for the 10GBASE-X standard, which has a throughput of ten Gigabits per second, the IP block has four channels that each supports data transfers of up to 2.5 Gigabits per second.
In a typical application, the programmable logic resource core circuitry sends a forwarded clock and data signals aligned with the forwarded clock to the channels in the IP block. A problem that often arises with the routing of the forwarded clock and the data signals is that the signals arrive at their respective channel at different times. This can be caused by the varying distances from the signal source in the programmable logic resource core circuitry to each channel in the IP block and also due to varying temperature changes.
The distance from the signal source in the programmable logic resource core circuitry to each channel in the IP block varies with each channel. The greater the distance, the longer the wire length and the more time that is needed to route a signal to a given channel. To minimize the difference in arrival times of the signals to each channel, additional wiring is typically added to the routing so that the wire lengths are substantially the same for each channel. However, the use of additional wiring increases the routing area. Furthermore, this approach does not take into account dynamic factors that can also cause delays in the routing of signals to the channels.
Signals can also reach their respective channel at different times due to varying temperature changes. Heat dissipation can vary with each channel depending on the application that the signals are used for and the location of the signal routing to each channel on the programmable logic resource. The greater the heat dissipation, the longer it takes for a signal to reach a given channel. To minimize heat dissipation, fans are sometimes installed to cool down a system. However, the fans may not produce the same cooling effect on the different areas of the programmable logic resource. Moreover, fans may not even be provided in a system.
In view of the foregoing, it would be desirable to provide circuitry that aligns data signals to a phase of a forwarded clock at each channel in a multi-channel communications protocol.